NXP reader chip
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MFRC50001T/OFE

MFRC500 belongs to the latest series of highly integrated reader IC, used for contactless communication 13.56 MHz. This series of card reader IC offers:

Excellent modulation and demodulation performance for passive contactless communication

Provide a variety of methods and protocols

Stitch compatible CLRC632, MFRC530, MFRC531 and SLRC400

Support all the ISO/IEC 14443 A hierarchy

Provide a stable and efficient demodulation receiver module/decoding circuit scheme of compatible transponder signals (see section 9.10 on page 30). Digital module management all the ISO/IEC 14443 A standard into frames and error detection (parity and CRC). In addition, it also supports fast Crypto1 security algorithm, used for authentication, MIFARE product (see section 9.12 on page 35).

Internal transmitter module (section 9.9 on page 27) can be directly driven for 100 mm close operation and design of the antenna, without any extra active circuit.

Parallel interface can be connected directly to any 8 bit microprocessors, to ensure that the card reader/terminal design flexibility.

Characteristics and advantages

3.1 introduction

A highly integrated analog circuit for demodulation and decoding card response

Buffer output drive can realize the antenna connection number with minimal external elements

The working distance of close to 100 mm

Support the ISO/IEC 14443 A standard 1 to 4 parts

Support MIFARE Classic protocol

Crypto1 and non-volatile internal memory key

Stitch compatible CLRC632, MFRC530, MFRC531 and SLRC400

Microprocessor parallel interface with internal address latch and IRQ lines

Flexible interrupt handling

Automatic detection of microprocessor parallel interface type

64 bytes sent and received the FIFO buffer

Hard reset function of low power consumption

Software triggered off mode

Programmable timer

Unique serial number

A user programmable launch configuration

Facing the bits and bytes oriented as a way for the frame

For analog, digital and transmitter module, independent power supply pins

To optimize the internal oscillator buffer against low phase jitter and has a 13.56 MHz quartz connection

Clock frequency filtering

Send is used to close and close to the application of the working voltage of 3.3 V

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